PANTA DP20 - Quad Full HD / 3D Full HD Display Processor

PANTA DP20 Block Diagram

The PANTA DP20 display processor is the backend module of a digital video path intended for use in real-time multi-display systems. The design has been optimized for high-end mobile devices by implementation of power reduction methods.

The PANTA DP20 provides support for 3 independent input layers with programmable size, offset and format. Also the output timing and resolution are fully programmable and give possibility for up to 8K display formats (e.g. Quad Full HD or DCI 4K).

The PANTA DP20 supports various YUV and RGB color spaces, also with several subsampling modes (4:4:4, 4:2:2, 4:2:0). Moreover, it implements advanced composition modes using layer and pixel alpha-blending methods.

The PANTA DP20 is equipped with the AMBA® AXI4 master interface to provide efficient, low-latency communication with the system memory. Flexible and easy programming of the display processor is provided by two AMBA® APB interfaces – one for general purpose and the other for secure access.

trustzone-rgb-tagPANTA DP20 is the only display controller to support ARM TrustZone technology.

  • Highlights
  • Benefits
  • Applications
  • Deliverables
  • Programmable custom display resolution up to 8191x8191 pixels
  • On-the-fly composition of up to 3 video and graphics layers
  • Interoperability with the ARM® TrustZone® environment
  • Plethora of supported RGB and YUV pixel formats
  • Support for 3D HDMI formats
  • HDMI and MIPI DPI compatible interface
  • AMBA® AXI4 read master interface
  • Programmable number of outstanding transactions (up to 32) and burst length (up to 256)
  • One pass operation to minimize the system memory bandwidth
  • Sub-frame latency
  • Power Save Mode via AXI Low power interface or by software
  • Programmable YUV to RGB color space conversion
  • Support for non-linear sRGB graphics processing and displaying
  • Pixel-level and layer-level alpha blending
  • Gamma and inverse-gamma correction
  • Output color adjustment with a programmable matrix of coefficients
  • Programmable display formats according to VESA or CEA standards, or specific user requirements
  • Significant CPU off-load from video processing tasks
  • Variety of operation modes and even more programmable parameters
  • AXI4-enabled high-performance and low latency solution
  • Compatibility with all ARM video and graphics processors
  • Support for the ARM® TrustZone® environment
  • High-end smartphones and tablets
  • Ultra-high resolution video processing SoC
  • Secure video systems
  • Multiple-display systems

Deliverables

  • Verilog source code
  • Synthesis support for Synopsys® and Cadence tools with a set of synthesis scripts
  • Simulation support for Mentor Graphics® and Cadence® tools with a set of scripts and macros
  • Extensive SystemC test bench
  • Documentation
  • 30 days of technical support 
  • 90 days of warranty against defects

Delivery Options

  • EDIF netlist for FPGA and low volume production
  • VHDL source code
  • IP core integration within a target SoC or FPGA embedded system
  • One-year maintenance
  • On-site support and training

PANTA DP20 Overview

PANTA DP20 Demo Board

Downloads

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